Conventional content addressable memories (CAMs) compare an input data word with all the words stored in the CAM. All of the stored words are simultaneously compared to the input data word over a few clock cycles. Because of the amount of computation that is done in parallel, CAM memories usually have very high peak current and high average power specifications. Relative to a CAM, an SRAM memory has much lower peak current and average power specifications. In addition, SRAM clock frequencies are usually higher than a comparable CAM.
It would be desirable to implement a memory that reduces peak current and average power, reduces area, and/or increases throughput (clock frequency) by implementing an SRAM with storage configuration and comparison circuitry.